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Data & statistics on Supply Current versus Output Frequency LVPECL and LVDS – 1396 results
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Peak-to-Peak Output Voltage vs. Frequency—LVPECL and LVDS (10 pF Load)
108 more results from this site ▶

Peak-to-Peak Output Voltage vs. Frequency—LVPECL and LVDS (10 pF Load)

www.analog.com/static/imported-files/data_sheets/AD9551.pdf

AD9551 LVPECL SUPPLY CURRENT (mA) LVDS (STRONG) LVDS (WEAK) 1k FREQUENCY (MHz) DUTY CYCLE (%) FREQUENCY (MHz) Rev. A | Page 12 of 40 ...
LVPECL AMPLITUDE (V p-p) LVDS (STRONG) LVDS (WEAK) FREQUENCY (MHz)

Apr 2009 | Analog Devices, Inc – 108 more results from this site
Original Url: http://www.analog.com/static/imported-files/data_sheets/AD9551.pdf
1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs
9 more results from this site ▶

1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs

www.datasheetcatalog.org/datasheet/maxim/MAX9310A.pdf

VOLTAGE (VOH - VOL) vs. FREQUENCY SUPPLY CURRENT vs. TEMPERATURE OUTPUT RISE/FALL ...
(mV) SUPPLY CURRENT (mA) RISE/FALL TIME (ps) tF tR TEMPERATURE (°C) FREQUENCY ...
2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed

Sep 2004 | datasheetcatalog.org – 9 more results from this site
Original Url: http://www.datasheetcatalog.org/datasheet/maxim/MAX9310A.pdf
Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs
5 more results from this site ▶

Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs

dodeca.gaw.ru/pdf/Maxim/interface/lvds/MAX9317-MAX9317C.pdf

Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs _______ ...
(mV) SUPPLY CURRENT (mA) FALL TIME RISE TIME TEMPERATURE (°C) CLK_ FREQUENCY (GHz ...
) OUTPUT AMPLITUDE (VOH - VOL) vs. CLK_ FREQUENCY OUTPUT RISE/FALL TIME vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE MAX9317 toc01 MAX9317 toc02 MAX9317 toc03 INPUTS OPEN

Aug 2002 | ????? ??????????????? ?????? ????????????????, – 5 more results from this site
Original Url: http://dodeca.gaw.ru/pdf/Maxim/interface/lvds/MAX9317-MAX9317C.pdf
HIGH-RELIABILITY LVPECL OR LVDS MINIATURE CLOCK OSCILLATORS 2.5 to 3.3Vdc - 40MHz to 320MHz
3 more results from this site ▶

HIGH-RELIABILITY LVPECL OR LVDS MINIATURE CLOCK OSCILLATORS 2.5 to 3.3Vdc - 40MHz to 320MHz

www.q-tech.com/assets/datasheets/QT93.pdf

QT93NP Parameters (LVDS Output) (LVPECL Output) 40MHz — 300.00MHz (*) Output frequency range (Fo) Supply voltage (Vcc) 3.3Vdc ± 5% 2.5Vdc ± 5% 3.3Vdc ± 5% 2 ...
QT93W and QT93P SERIES QT93W and QT93P SERIES HIGH-RELIABILITY LVPECL OR LVDS MINIATURE CLOCK OSCILLATORS 2.5 to 3.3Vdc - 40MHz to 320MHz Q-TECH CORPORATION Packaging Options • Standard packaging in anti-static plastic tube (60pcs/tube) • Tape and Reel ...
HIGH-RELIABILITY LVPECL OR LVDS MINIATURE CLOCK OSCILLATORS 2.5 to 3

Jan 2010 | | Q-Tech Corporation – 3 more results from this site
Original Url: http://www.q-tech.com/assets/datasheets/QT93.pdf
Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four
3 more results from this site ▶

Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four

datasheet.eeworld.com.cn/pdf/28072,MAXIM,MAX9378EUA.pdf

input voltage |VID| = 0.2V, VCM = 1.2V, input frequency = 500MHz, outputs terminated ...
= +25°C, unless otherwise noted.) PROPAGATION DELAY vs. TEMPERATURE SUPPLY CURRENT vs. FREQUENCY OUTPUT AMPLITUDE vs. FREQUENCY MAX9377/78 toc01 MAX9377/78 toc02 MAX9377/78 ...
voltages are referenced to ground except VTHD, VID, VOD, and ∆VOD. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters production tested at TA = +25°C and guaranteed by design

Jan 2000 | datasheet.eeworld.com.cn – 3 more results from this site
Original Url: http://datasheet.eeworld.com.cn/pdf/28072,MAXIM,MAX9378EUA.pdf
LVPECL, LVDS, HCSL, dual output CMOS, diff CMOS, dual output SSTL, diff SSTL
13 more results from this site ▶

LVPECL, LVDS, HCSL, dual output CMOS, diff CMOS, dual output SSTL, diff SSTL

www.silabs.com/Marcom%20Documents/Resources/TimingSelectorGuide.pdf

specifications including frequency, supply voltage, and output format. FEATURES:: • Quartz ...
LVPECL, LVDS, HCSL and SSTL options • Driver stopped, tristate, and power down ...
°C) ± 150 (0-70 °C) ± 250 (0-85 °C) PART NUMBER TYPE FREQUENCY OUTPUT FORMAT FOOTPRINT Si500S 0.9 to 200 MHz ± 20 ppm typ CMOS, SSTL 3.2 x 5 mm 4-pad XO LVPECL, LVDS, HCSL, dual output CMOS, diff CMOS, dual output SSTL, diff SSTL Si500D 0.9 to 200 MHz ± 20

Oct 2010 | www.silabs.com – 13 more results from this site
Original Url: http://www.silabs.com/Marcom%20Documents/Resources/TimingSelectorGuide.pdf
And differential output voltage levels (Table 37) for Rev. 0. Published new quiescent current numbers (Table 33). Updated pull-up and pull-down resistor strengths (Table 32). Added LVDCI_DV2 and LVPECL standards (Table 36 and Table 37). Changed CCLK setup time (Table 65 and Table 66).
2 more results from this site ▶

And differential output voltage levels (Table 37) for Rev. 0. Published new quiescent current numbers (Table 33). Updated pull-up and pull-down resistor strengths (Table 32). Added LVDCI_DV2 and ...

china.origin.xilinx.com/support/documentation/data_sheets/ds099.pdf

. Improved the DFS minimum and maximum clock output frequency specifications (Table 59 ...
quiescent supply current (Table 33) and DLL timing. Revised VIN maximum rating (Table 27). Added power-on requirements (Table 29), leakage current number (Table 32), and differential output voltage levels (Table 37) for Rev. 0. Published new quiescent current ...
(Table 32). Updated quiescent current numbers and added information on power-on and surplus current (Table 29). Added equivalent resistance values for internal pull-up

Nov 2007 | Xilinx FPGA/CPLD ?????? – 2 more results from this site
Original Url: http://china.origin.xilinx.com/support/documentation/data_sheets/ds099.pdf
And differential output voltage levels (Table 37) for Rev. 0. Published new quiescent current numbers (Table 33). Updated pull-up and pull-down resistor strengths (Table 32). Added LVDCI_DV2 and LVPECL standards (Table 36 and Table 37). Changed CCLK setup time (Table 65 and Table 66).
3 more results from this site ▶

And differential output voltage levels (Table 37) for Rev. 0. Published new quiescent current numbers (Table 33). Updated pull-up and pull-down resistor strengths (Table 32). Added LVDCI_DV2 and ...

www.ccse.kfupm.edu.sa/~ahmadsm/teaching/coe203-082/spartan3.pdf

. Improved the DFS minimum and maximum clock output frequency specifications (Table 59 ...
quiescent supply current (Table 33) and DLL timing. Revised VIN maximum rating (Table 27). Added power-on requirements (Table 29), leakage current number (Table 32), and differential output voltage levels (Table 37) for Rev. 0. Published new quiescent current ...
(Table 32). Updated quiescent current numbers and added information on power-on and surplus current (Table 29). Added equivalent resistance values for internal pull-up

May 2007 | www.ccse.kfupm.edu.sa – 3 more results from this site
Original Url: http://www.ccse.kfupm.edu.sa/~ahmadsm/teaching/coe203-082/spartan3.pdf
CMOS, LVDS CMOS, LVDS, LVPECL
17 more results from this site ▶

CMOS, LVDS CMOS, LVDS, LVPECL

www.arrownac.com/offers/analog-devices/rf/pdf/RF_Source_Winter2010.pdf

or DCO Max Output Frequency (MHz) Part Number Number of Outputs Number of Dividers I/O Interface Output Logic Package CML, PECL-compliant CMOS, HSTL LVDS, LVPECL, CMOS AD9540 ...
Frequency (MHz) Part Number I/O Interface Output Logic Package AD953 AD955 CMOS, LVDS

Dec 2009 | Arrow Electronics - North American Components (NAC) – 17 more results from this site
Original Url: http://www.arrownac.com/offers/analog-devices/rf/pdf/RF_Source_Winter2010.pdf
VCCA = VCCD = +3.3V ±10%; VCCO = +2.5V ±5% or +3.3V ±10%, RL (LVDS) = 100Ω across the output, RL (LVPECL) = 50Ω into VCCO–2V; TA = –40°C to +85°C, unless otherwise stated.
38 more results from this site ▶

VCCA = VCCD = +3.3V ±10%; VCCO = +2.5V ±5% or +3.3V ±10%, RL (LVDS) = 100Ω across the output, RL (LVPECL) = 50Ω into VCCO–2V; TA = –40°C to +85°C, unless otherwise stated.

www.micrel.com/_PDF/HBW/sy89537l.pdf

Output Frequency Range Internal VCO Frequency Range LVPECL Output Banks (0–3), Bank-to-Bank LVDS Output Banks (0–2), Bank-to-Bank Part-to-Part Skew Condition Note ...
mV mV LVDS Output DC Electrical Characteristics VCCA = VCCD +3.3V ±10%, VCCO ...
Cycle Output Rise/Fall Time (20% to 80%) LVPECL Output Rise/Fall Time (20% to 80%) LVDS Note 13 See “PLL Stability” Table BW tDC tr, tf See “Synchronization” t

Jan 2007 | Micrel – 38 more results from this site
Original Url: http://www.micrel.com/_PDF/HBW/sy89537l.pdf
Related searches: power supply current versus frequency, delay time versus supply voltage, lo return loss versus lo frequency, output swing versus supply voltage, supply current versus sampling rate

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